1) Field of the Invention
This invention pertains to the field of semiconductor memory devices, and more particularly, to a nonvolatile memory cell produced of semiconductor transistor structures common to semiconductor logic devices.
2) Background of the Related Art
Semiconductor memory devices may be largely divided into Random Access Memories (RAMs) and Read Only Memories (ROMs). RAMs, also referred to as volatile memories because the stored data is destroyed with the passage of time upon removal of the power supply, allow rapid data storage and data retrieval. ROMS, also referred to as nonvolatile memories because they retain data once it is entered, typically have slower data storage and data retrieval times.
One popular type of ROM is the Electrically Erasable Programmable Read Only Memory (EEPROM) in which data is electrically programmed and erased. A flash EEPROM, which is electrically erasable at high speed without being removed from a circuit board, offers the advantages of a simple memory cell structure, cheap cost, and no need for a refresh signal to retain the data.
EEPROM cells are largely divided into two types: a NOR type EEPROM and a NAND type EEPROM.
FIG. 1 shows a circuit diagram for a NOR-type flash EEPROM cell 100. A metal oxide semiconductor (MOS) transistor 120 is provided with a floating gate 110 and a control gate 160. The floating gate 110 may be programmed with a charge according to the data to be stored in the memory cell 100. Data is read by selecting the transistor on a word line connected to the control gate 160 and detecting the presence or absence of a current through the transistor on a bit line 170 connected to one terminal of the device.
A number of different memory cell structures have been used for a nonvolatile memory device. FIG. 2 shows one configuration of a NOR-type Flash EEPROM cell 200 according to the prior art. The memory cell 200 comprises a semiconductor substrate 205 having first and second impurity regions 225 and 235 formed in a top surface of a well 202. The first impurity region 225 is connected with a bit line 270 of the memory device 200, while the second impurity region 235 is connected with ground potential. A first oxide later 230 is deposited on the top surface of the semiconductor substrate where the first and second impurity regions 225 and 235 are formed.
A floating gate 210 is formed on the first oxide layer 230 above and between the first and second impurity regions 225 and 235. A control gate 260 is also formed above and between the first and second impurity regions 225 and 235. A portion of the control gate 260 is formed above the floating gate 210, separated by a second oxide layer 250. The floating gate 210 and the control gate 260 may each be formed of conductive polysilicon layers.
To program the EEPROM device 200 with a potential V.sub.p, the word line connected with the control gate 260 is supplied with a large positive potential V.sub.PGM (e.g., V.sub.PGM =12.5 Volts). This causes an injection of electrons onto the floating gate 210. To read the data from the cell 200, a lower positive voltage V.sub.cc, (e.g., 5 volts) is applied to the control gate while the bit line is supplied with a smaller positive voltage (e.g., 1-2 volts). Data 0 or 1 is read from the cell 200 according to the presence or absence of a current path through the cell, relying on the principle that the threshold voltage V.sub.th of the cell is changed to a voltage greater than +5V when electrons are stored in the cell, while the threshold voltage V.sub.th is about 1.5V when electrons are not stored on the floating gate. Data may be erased though exposure to ultraviolet light radiation, or through a separate erase gate (not shown).
Disadvantageously, these prior art nonvolatile memory cell structures are not readily adaptable to integration in a logic device such as a gate array. For example, the EEPROM cell 200 requires two polysilicon layers or more, whereas the typical gate array process uses a single polysilicon process. Yet, it is desirable to provide nonvolatile memory cells in a gate array device.
Accordingly, it would be advantageous to provide a nonvolatile memory cell which may be easily integrated into a semiconductor logic device. It would also be advantageous to provide a nonvolatile memory cell which may be easily integrated into a gate array logic device. It would be further advantageous to provide a nonvolatile memory cell which can use the same process technologies and array structures which are used to manufacture gate array logic circuitry. Other and further objects and advantages will appear hereinafter.